This is a major milestone in the effort to double the data rate of the PCI Express specifications while maintaining backwards compatibility and marks the final technical draft of the standard.
The PCIe 6.0 specification was announced in June 2019 with the aim of a two year development process. Version 0.9 is the final draft of the specification wherein members perform internal reviews of the technology for their essential patents. No additional functional changes are expected during this time.
The technology is intended to provide more performance in data-hungry server, client, embedded, cloud and edge designs as an ugrade path for the PCIe 5.0 controllers that are now coming to market.
The PCIe 6.0 specification includes a 64 GT/s data rate and up to 256 GB/s via x16 configuration, doubling the bandwidth of the PCIe 5.0 specification. It uses PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and makes use of existing 56G PAM-4 technology in the industry with FLIT (flow control unit)-based encoding and low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency.
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